As will be appreciated by those skilled in the art, semiconductor data storage circuits struck by high energy particles in a space environment can lose data due to the ionizing effects of the impact. The data storage circuits can include latches which can be used as registers in a processor or as a storage cell in a memory. These latches are susceptible to the energized particle strikes. The processors including the latches can be used in satellites and in other computer equipment which can be placed in environments which are highly susceptible to radiation. A processor in a satellite in a space environment, can be exposed to a radiation-induced soft error or single event upset (SEU) when a node of the latch is struck by high energy particles. A soft error or SEU typically is caused by electron-hole pairs created by, and along the path of, a single energetic particle as it passes through an integrated circuit. Should the energetic particle generate the critical charge in the critical volume of a latch, then the logic state of a node of the latch and thus, the contents of a register can be upset. This critical charge, by definition, is the minimum amount of electrical charge required to change the logic state of the register. The critical charge may also enter the latch through direct ionization from cosmic rays.
SEU typically results from alpha particles (helium nuclei), beta particles or gamma rays impacting a low-capacitance node of a semiconductor circuit. An example of an SEU of an inverter is illustratively described. An inverter can include a PMOS transistor and an NMOS transistor with their drains coupled together. The inverter can be used to generate complementary signals. When an alpha particle strikes bulk semiconductor material in the PMOS transistor, it can generate electron-hole pairs. Assuming that the NMOS transistor is on and that the PMOS transistor is off, the holes which collect at the coupled drain can change the voltage at an output node coupled to the drains from a logic low to a logic high. Electrons will diffuse toward the circuit supply voltage through the PMOS. A charge generating energetic particle hit on the NMOS transistor has the opposite effect, with positive charges drifting towards ground and negative charges collecting at the drain output, thus possibly changing the logic state of the inverter with its NMOS transistor off and its PMOS transistor on. In P-substrate, bulk CMOS technologies with PMOS devices formed in an NWELL, the effect of a charge particle hitting an NMOS transistor diffusion is typically worse than when a charged particle hits a PMOS transistor diffusion in an NWELL.
As will be appreciated by those skilled in the art, when a heavy ion traverses a node within a latch, the ion can force the node from its original state to an opposite state for a period of time. This change of state can be due to the charge that the heavy ion deposits as it passes through the silicon of a MOS transistor of the latch. If this node is held in the opposite state for a period of time longer than the delay around a feedback loop of the memory cell, the cell can switch states and the stored data can be lost. The period of time which the node is held in its opposite state can depend on several factors including, the charge deposited, the conductance of the transistors of the latch and the delay around the feedback loop of the latch.
Conventional designs that add resistive coupling between stages of a latch or bi-stable CMOS circuit have been used to provide hardening (i.e. immunity) against these so called single event upset (SEU) phenomena. The interstage resistive coupling can be effective in providing hardening against upsets from high energy particles, but this approach increases the time to write data into the element.
Resistive coupling can be used to radiation harden a CMOS static random access memory (RAM) cell; see for example U.S. Pat. No. 5,053,848, the contents of which are incorporated herein by reference in their entirety. The RAM cell includes lightly doped polysilicon resistors forming feedback paths between two CMOS invertors.
Metal oxide semiconductor (MOS) originally described transistor gates which were fabricated using metal over a thin oxide layer. A MOS transistor can also be commonly referred to as a field effect transistor (FET) or as a MOSFET. Today the term is applied more broadly to include transistors with gates of polysilicon over oxide. NMOS, PMOS and CMOS are three exemplary types of MOS technology. "NMOS" refers to n-type MOS transistors. "N-type" refers to a dopant introduced into silicon to enhance its ability to conduct electrons, which are negatively charged particles. "PMOS" uses a p-type dopant which enhances the conduction of electron "holes," which are positive charges. "CMOS" means complementary MOS and involves the fabrication of both PMOS and NMOS devices on a single substrate. Usually, PMOS devices are fabricated in n-type wells while NMOS devices are formed within primarily p-type substrate. NMOS has long prevailed over PMOS as a technology of choice, while CMOS has advanced rapidly as advantages of combining PMOS and NMOS have often outweighed the complexity of combining them. A PMOS can also be referred to as a PFET and an NMOS as an NFET.
FIG. 1 illustrates a conventional unhardened register element 100, typically used in commercial designs. CMOS transistors, including PFET 104 and NFET 106 having source-drain regions coupled together, and PFET 116 and NFET 118 also having source-drain regions coupled together, are used to access data storage invertor 124 including PFET 108 and NFET 110, and data storage inverter 126 including PFET 112 and NFET 114, and to provide regeneration feedback loop 128. When signals CLK 120 and CLK* 122 are active, write access to the data storage element is provided through an input D 102 and CMOS transmission gate including transistors PFET 104 and NFET 106. With CLK 120 and CLK* 122 active, the feedback transistors, PFET 116 and NFET 118 are turned off, allowing the D input 102 to force node 132, 136 and 138 to proper logic levels. When CLK 120 and CLK* 122 are inactive, access through PFET 104 and NFET 106 ceases, and the regenerative feedback 128 from node 134 to node 132 is completed by the CMOS transmission gate including transistors PFET 116 and NFET 118. An approach which can be used to radiation harden a circuit can include an isolation circuit. One isolation circuit is described in U.S. Pat. No. 5,525,923, issued to Bialas, Jr., et al., of common assignee the present invention, the contents of which are incorporated herein by reference in their entirety. The Bialas et al. patent describes an exemplary isolation circuit including a plurality of resistors which are used to induce resistive delay.
Other techniques for providing SEU immunity, which do not rely on resistive induced delay for hardening, can also be used. These techniques can provide a high level of SEU immunity without adversely affecting the write setup time as can resistive hardening. However, these other techniques can increase transistor count, circuit complexity, and require more silicon area.
While the use of resistor elements to enhance SEU immunity of a latch is known, commercial technology does not readily provide for a resistor forming process. Using polysilicon resistor material which has a high temperature co-efficient of resistance creates processing problems for circuit operation over a wide range of temperatures. In other applications such as gate arrays, a personalization step requiring the formation of polysilicon resistors is not practical. What is needed is a radiation hardened latch that eliminates write time performance penalties, is process insensitive and tracks transistor performance with temperature, and can be fabricated in high density.